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Knowledge Centers

• Knowledge Center
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  • Troubleshooters
    • Usage Guidelines
    • Software Licensing
    • Simulating with ModelSim
    • Timing Analysis
    • PLL Loss of Lock
    • FPGA Configuration
    • JTAG Config & ISP
    • Parallel Flash Loader
    • Jam STAPL, JBC & SVF ISP
• PowerPlay Power Analyzer
• On-Chip Debugging
• Installation and Licensing
• External Memory
• Power Management
• Board Design Guidelines
• Configuration Center
• Design Software Resource Center

Device Support

• Stratix V (E, GX, GS, GT)
• Stratix IV (E, GX, GT)
• Stratix III
• Stratix II/Stratix II GX
• Stratix/Stratix GX
• Arria V (GX, GT, SX, ST)
• Arria II (GX and GZ)
• Arria GX
• Cyclone V (E, GX, GT, SE, SX, ST)
• Cyclone IV (E and GX)
• Cyclone III
• Cyclone II
• Cyclone
• MAX V
• MAX II
• MAX 3000A
• MAX 7000
• HardCopy IV
• HardCopy III
• HardCopy II
• HardCopy Stratix
• HardCopy APEX

Device Support (cont'd)

• Downloads
  • Device Pin-Out Files
  • Pin Connection Guidelines
  • BSDL/BST
  • Spice Models
  • IBIS Models
  • Schematic Review Worksheets
  • Layout Review Worksheets
  • IBIS Models
  • Cadence PCB Libraries
  • Mentor Graphics PCB Libraries
  • Gerber Files
• Power
  • Early Power Estimators
  • Programming Center
  • Programming Tools
• I/O
  • I/O Features
  • I/O Specifications
  • HotSocketing
• PLL & Clock Management
  • PLL Clock Management Features
  • Jitter Information
  • Clock Networks
• Packaging & Board Design
  • Package and Thermal Resistance
  • Sockets and Layout
  • Design and Manufacturing Guidelines
• Quality & Reliability
  • Moisture Sensitivity Level Calculator
  • Certifications
  • Environmental Policy Information
  • PCNs and Advisories
  • Reliability Report
  • JEDEC Compliance
  • Single Event Upsets
  • Failure Analysis

Design Software Support

• Quartus II
• Qsys
• SOPC Builder
• ModelSim-Altera
• MAX+PLUS II
• OS Support
• Driver Installation
• Download
• Licensing
• Quartus II Help
• Resource Centers
  • Installation and Licensing
  • Scripting
  • Board Design and I/O
  • Design Entry and Planning
  • Synthesis and Netlist Viewers
  • Incremental Compilation
  • Optimization
  • TimeQuest Timing Analyzer
  • Classic Timing Analyzer
  • Simulation and Verification
  • On-chip Debugging
  • HardCopy Design
  • EDA Tool Support

Intellectual Property (IP) Support

• Nios II Embedded Design Suite
• Nios II Development Kits
• DSP Builder
• DSP IP Cores
• DSP Development Kits
• PCI Express IP Cores
• POS-PHY Level 4
• SDI
• Triple Speed Ethernet
• 10-Gbps Ethernet
• RapidIO

• Development Kits/Cables
• Design Examples
• Literature and Technical Documentation
• mySupport/myAltera

Downloads and Licensing Support

• Software
  • All Downloads
  • Quartus II Subscription Edition
  • Quartus II Web Edition (Free)
  • MegaCore IP Library
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  • ModelSim-Altera Starter Edition
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  • DSP Builder
  • OS Support
• Licensing
  • Get and Manage Licenses
  • Licensing FAQ
  • License Daemon Downloads
• Programming Software
  • Quartus II Programmer
  • Jam™ STAPL Software
• Drivers
  • Cable and Adapter Drivers
• Board Layout and Test
  • BSDL/BST
  • Spice Models
  • IBIS Models
  • Schematic Review Worksheets
  • Layout Review Worksheets
  • IBIS Models
  • Cadence PCB Libraries
  • Mentor Graphics PCB Libraries
  • Gerber Files

User Communities

• Altera Forum
• Altera Wiki

Device Type

• CPLDs
• FPGAs
• ASICs
• SoCs/Processors

• Compare Altera Devices

FPGAs

• FPGA Overview
• Stratix V (E, GX, GS, GT)
• Stratix IV (E, GX, GT)
• Stratix III (L and E)
• Stratix II GX
• Stratix II
• Stratix GX
• Stratix
• Arria V (GX, GT, SX, ST)
• Arria II (GX and GZ)
• Arria GX
• Cyclone V (E, GX, GT, SE, SX, ST)
• Cyclone IV (E and GX)
• Cyclone III
• Cyclone II
• Cyclone

• Serial Configuration

CPLDs

• MAX V
• MAX II (and G, Z)
• MAX 7000
• MAX 3000A

ASICs

• HardCopy V
• HardCopy IV (E and GX)
• HardCopy III
• HardCopy II
• HardCopy Stratix

Device-Specific Offerings

• RoHS Compliance
• Extended Temperature
• Enhanced Temperature
• Military Temperature

SoCs/Processors

• Processor Selector

Processors

• ARM^® Cortex^™-A9 MPCore Processor
• ARM Cortex-M1 Processor
• Freescale ColdFire-V1 Processor
• Intel^® Atom^™ Processor E6x5C Series
• MP32 Processor (MIPS)
• Nios II Processor

SoC FPGAs

• SoC FPGA Overview
• Arria V (SX and ST)
• Cyclone V (SE, SX, ST)

• Altera Embedded Alliance

Design Software

• Quartus II Subscription Edition
• Quartus II Web Edition
• ModelSim-Altera
• Nios II Embedded Design Suite
• DSP Builder
• FPGA and CPLD Design Flow
• HardCopy ASIC Design Flow
• ASIC Users
• Xilinx ISE Users
• MAX+PLUS II Users
• EDA Partners
• Ordering
• Downloads
• Licensing

Intellectual Property (IP)

• All Intellectual Property
• All Reference Designs
• Bridges
• Configuration and Programming
• Connectors and Converters
• DSP
• Embedded Processors
• Interface Protocols
• Memory and Controllers
• Optical Network Transport
• Peripherals
• PLL
• Qsys Interconnect
• Verification
• Designing with IP
• IP Base Suite
• IP Certifications
• System Design
• Download and Evaluate IP
• Request IP
• About AMPP Program
• IP Partners

Development Hardware

• Development Kits
• Daughtercards
• Education Boards (University Program)
• Board Partners
• Download Cables
• Programming Adapters

Design and Support Services

• Design Services Partners
• Altera Professional Services

Documentation

• All Documentation
• Altera Product Catalog (PDF)
• Technical Email Updates

• Automotive
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• Test and Measurement
• Wireless
• Wireline

• Digital Signal Processing (DSP)
• External Memory

• Transceivers

• Signal Integrity

Training Courses

• Course Catalog
• Class Schedule
• Curricula
  • CPLD Designer
  • FPGA Designer
  • ASIC-to-FPGA Designer
  • HardCopy Designer
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  • SOC Designer
  • Embedded HW Designer
  • Embedded SW Designer
  • Transceivers
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University Program (UP)

• Resource Centers
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  • Quartus II University Interface Program (QUIP)
• UP Support Overview
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• Contact University Program

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