Military application functions that were once restricted to ASIC designs or microprocessor systems now benefit from the shorter design cycle times and simpler hardware verification processes of an FPGA. Our 40-nm Arria® II FPGAs, in particular, are ideal for military applications. Arria II FPGAs feature integrated transceivers at speeds up to 6.375 Gbps, rich memory and logic resources, and digital signal processing (DSP) capabilities.
Figure 1 conveys the growing list of military electronics design domains that can be addressed with programmable logic devices.
Figure 1. Design Domains
The effect is a greater potential for system-on-chip (SoC) integration with an emphasis on tool flow and intellectual property (IP) reuses. This is especially true given the more difficult verification and rigorous test requirements of military electronics systems.
While the number of technical requirements that must be considered by systems engineers cannot be easily summarized, there are three large initiatives in military electronics technology that are addressed by Arria II FPGAs: reductions in size, weight, and power (SWaP).
The simplest approach to reducing SWaP is integrating many subsystems into a single chip. While this can be enabled through robust systems engineering processes and workflow controls, it increases the importance of open systems designs and anti-tamper technologies for FPGAs. To see effiiciency improvements in new SoC designs, design re-uses must be a fundamental part of systems design flow.
The Altera® design flow makes standard interface IP available throughout the design entry process. This includes the high-speed Serial Rapid IO® standard, both soft and hard PCI Express cores, Gigabit Ethernet, and 10 Gigabit Ethernet cores optimized for Altera’s transceiver technology. For your own internally developed IP cores, encapsulation of these cores in Altera’s SOPC Builder is a simple process that allows for easy archival and retrieval of important re-usable logic blocks.
While there are plenty of reasons to focus on the features and capabilities of Arria II FPGAs, cost conscious military systems designers must also evaluate design flow. Design time productivity for programmable devices includes verification, debug, and compile times, which can all present significant schedule risks in defense programs. As a result, Altera has invested significantly in compile-time improvements, multiprocessor synthesis support, and incremental compile technology to include team-based “bottoms up" design, and SOPC Builder for fast system bus generation.
