Military Webcasts and Videos | |
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Mitigating Soft Errors in DRAM Through Error Correction Code on SoC FPGAs This webcast looks at how mitigating soft errors through error correction code (ECC) can improve your embedded designs. Hans Spanjaart, Sr. Technical Marketing Manager |
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Implementing FPGA Design with OpenCL – A Future Look Watch this webcast to find out about a new technology for FPGAs called OpenCL. You'll learn about the market drivers and embedded technology enablers, the benefits of using FPGAs as hardware accelators, and how OpenCL fits in an FPGA-based design environment. Jordon Inkeles, Sr. Manager, Software and DSP |
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Jump-Start Software Development with the SoC FPGA Virtual Target Watch this 7-minute video to find out how you can start software development with the Altera® SoC FPGA Virtual Target. You’ll see how you can get better visibility and control for debugging, do statistical and trend-based performance analysis, and use industry-standard tools to develop and debug your design. Stephen Lim, Product Manager |
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Accelerate Your Video Design with an FPGA and IP Cores Watch this webcast to find out how a customizable solution and quick intellectual property (IP) integration helps you build your video design faster – whether for simple format conversion or advanced digital video processing. Richard Yang, Sr. Product Marketing Engineer |
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5 Reasons to Use a Soft-Core MIPS Processor in Your Next Custom Design Watch this video to learn five reasons why you should use a soft-core MIPS processor in your next custom design. You'll get insights about the MP32 processor, the first 100 percent MIPS-compatible soft processor available for Altera® FPGAs and HardCopy® ASICs. Cal Ruben, Applications Engineer, Embedded Technology |
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Sneak Peek: Industry's First 28-nm High-End FPGA Running at 14.1 Gbps Watch this video to see the progress of the Stratix V FPGA characterization process, as well as 14.1-Gbps transceiver performance. Stratix V FPGAs are the industry's first 28-nm high-end FPGAs. Salman Jiva, Applications Manager |
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Make Music and More with Low-Cost, Low-Power CPLD Dev Kit This video demonstrates the various capabilities of the MAX V CPLD Development Kit. Available for only $74.95, the kit gives you the resources to evaluate the MAX V CPLD and to prototype CPLD applications. Jenny Gendron, Altera |
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Enhance Your Productivity with Faster Design Compile Times When choosing your FPGA design software, be sure to consider compile time, a key productivity advantage. In this webcast, you'll learn how Altera's Quartus® II design software delivers a 2X to 3X compile time advantage over competitive software. Richard Yang, Product Marketing Engineer |
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Lower Power and Boost System Bandwidth on 28-nm FPGAs Learn about key innovations in Stratix® V FPGAs that address bandwidth and power challenges in high-end systems designs. Embedded HardCopy Blocks, power-efficient 28-Gbps transceivers, and software power optimization are just a few of the features that will help you balance bandwidth, power, and cost requirements. Frank Yazbeck, Senior Technical Marketing Staff |
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Achieving 1-TFLOPS Performance with 28-nm FPGAs Watch this webcast to learn how Altera’s 28-nm Stratix® V FPGA, with its unique variable-precision digital signal processing (DSP) architecture,can deliver 1 TFLOPS performance. This architecture combines the implementation efficiency of fast Fourier transforms (FFTs) and finite impulse response (FIR) with the best support for higher precision and floating-point signal processing. Michael Parker, DSP Technical Marketing Manager |
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