Altera provides a combination of cost-effective silicon and building block intellectual property (IP) to address the high volume, cost-sensitive access market.Depending on the performance and feature requirements of the access platform, Altera offers a wide silicon portfolio to choose from, including the low-cost Cyclone FPGA Series, the midrange Arria FPGA Series, and the high-performance Stratix FPGA Series that offers a cost reduction path to HardCopy® ASICs. In addition, Altera provides robust solutions to enable quick time-to-market and cost effective implementations of:
Overview
Access networks are considered the “last mile” of delivering connectivity from communication providers to home users. Digital Subscriber Line (DSL), Passive Optical Network (PON), and Cable are the three main broadband access technolo;gies deployed by different operators in different regions of the world.
DSL uses traditional phone lines to transmit the data. There are a variety of DSL technologies such as Asymmetric Digital Subscriber Line (ADSL) and Very High Speed Digital Subscriber Line (VDSL), offering different data bandwidths. Techniques such as channel bonding and vectoring can be used to increase the DSL bandwidth.
PON uses a point-to-multipoint optical fiber network to transmit data. There are multiple flavors of PON technologies as well, with the most popular being EPON and GPON.
Cable uses existing cable television infrastructure to provide broadband Internet access, and it is mostly adopted in North America and Europe. The standard used for cable broadband access is Data Over Cable Service Interface Specification (DOCSIS).
Altera and our partners can support your development methodology, whether you want to develop your access application in house or buy off-the-shelf IP solutions. A programmable platform allows you to scale your design across applications, features, and data rates. You will be able to swiftly incorporate new features, operator requirements, and density variations.
Typical Access Line Cards
Figure 1 shows a generic multi-service access platform with both DSL and PON line cards. The client side processing portion of the access line card varies depending on the access technology. It could be a DSL chipset, a PON MAC or DOCSIS MAC. However, regardless of the access technology, packet processing and traffic management functions are needed to process the aggregated end-user flows and provisioning per different QoS requirements from different operators in different applications.
Figure 1. Generic Multi-Service Access Platform Block Diagram
A combination of Altera’s multi-threaded RISC-based soft datapath processor and hardware acceleration blocks implemented in FPGA fabric can be well suited to perform the Layer 2 to Layer 4 packet processing functions needed for access platforms such as classification, table look-up, policing, filtering, and packet forwarding. As the service providers try to maximize end user experience by having the ability to differentiate services of each user and more and more users get aggregated onto the same pipe, it is very important to be able to enforce the service level agreement (SLA) per user to guarantee fair bandwidth allocation. Altera’s FPGA-based traffic management solutions provide you the flexibility and scalability needed to satisfy different QoS requirements.
Altera Solutions in Access
- Ethernet Solutions
- Packet Processing
- Traffic Management
- Backplane Switch Fabric
- Protocol Bridges
- Fordward Error Correction
- Channel Bonding
Altera Design Advantages in Access
- Flexibility - Using Altera FPGAs to implement the next-generation access systems provides the flexibility to build future-proof products, design unique features to differentiate against competitors, and quickly make modifications to accommodate different operator requirements, while Altera provides the building block IPs needed to help accelerate the internal development effort.
- System Integration - As operators move to next-generation access systems, they are not only looking for higher bandwidth and higher functionality, but are also constantly driving for lower cost and power. To address these challenges, the 28-nm Stratix V FPGA family enables an unprecedented level of system integration on one device. The combination of its abundant resources, its very robust 12.5-Gbps transceivers with built-in XG-PON1 and 10G-EPON burst mode and 10GBase-KR backplane support capability, and its high-performance external memory interfaces provides a single-chip solution for next-generation access line cards. These capabilities help save BOM cost, board space, and system power.
- Cost Reduction Path - Hardcopy ASICs is a unique offering from Altera that enables seamless design migration from FPGA to HardCopy ASICs with the use of only one tool and one methodology. Once the next-generation access design stabilizes and volume starts to ramp, migration to an Altera’s HardCopy ASIC can help reduce the cost and power with a quick turn-around time.
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