Configuration via Protocol (CvP) is a configuration scheme that allows you to configure the FPGA fabric via the PCI Express® (PCIe®) interface for Altera’s 28-nm Arria® V and Stratix® V FPGAs. The autonomous PCIe hard intellectual property (IP) allows the embedded PCIe core to operate before the FPGA is fully configured. This enables the FPGA devices to easily meet the PCIe wake-up time requirement.
Table 1 provides links to the documentation and resources that can help you implement CvP in your system.
| Table 1. CvP Documentation and Resources | |
| Resource | Description |
|---|---|
| Documentation | |
| Configuration via Protocol (CvP) Implementation in Altera® FPGAs (PDF) user guide | This user guide discusses the modes, topologies, features, design considerations, and software for CvP. |
| FPGA Configuration via Protocol (PDF) white paper | This white paper describes how CvP helps your system meet the PCIe wake-up time requirement in 28-nm FPGAs. |
| Training Courses | |
| CvP Implementation in Altera FPGAs (online course) | This class allows you to make design decisions based on the CvP features, software support, and software driver capability. You will also learn the design considerations for CvP in an open and closed system. The online training course will be available by end of Q4 2011. |
| Driver and Tools | |
| Software driver code | This is the open source code of the software driver developed on top of the lower level WinDriver application programming interface (API) for performing CvP operations. You can use this open source code as a reference to customize your own driver to perform CvP operations on your system. The open source code will be available by end of Q4 2011. |
