Fast Passive Parallel Configuration

To meet the continuously increasing demand for faster configuration times, Altera^® devices offer fast passive parallel (FPP) configuration with different data bus widths: 8-bit data width (FPP x8), 16-bit data width (FPP x16), and 32-bit data width (FPP x32). The FPP x16 and FPP x32 schemes are supported only in Stratix^® V devices.

For more information, refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.

Configuration Methods

• Using an enhanced configuration (EPC) device
  • Altera Configuration Devices (PDF)
  • Enhanced Configuration Devices data sheet (PDF)
• Using a microprocessor
• Using a MAX^® II CPLD as an external host

Embedded Solution

• Configuring the MicroBlaster^TM FPP Software Driver white paper (PDF)
  • Portable software driver used to configure an FPGA via an FPP interface
  • Source code (ZIP) available for porting to an embedded system or other platform

Application Note

• AN 386: Using the Parallel Flash Loader with the Quartus^® II Software (PDF)
  • Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the FPGA

Reference Design

• MAX Series Configuration Controller Using Flash Memory white paper (PDF)
  • Using a MAX or MAX II CPLD as a configuration controller to configure Altera FPGAs from flash memory
  • Source code (ZIP) in Verilog and VHDL