Altera provides a complete IEEE 802.3 10-Gbps Ethernet standard-compliant physical interface/media access control (PHY/MAC) FPGA-based or HardCopy® ASIC-based solution for a variety of chip-to-chip, backplane, and cable applications using the XAUI (10GBASE-X and XGXS) interface protocol. The XAUI solution include Altera® devices with integrated transceivers, development kits, intellectual property (IP) from Altera and MorethanIP, collateral, and test data. These solutions enable simple, fast protocol implementation, which reduces design risk, shortens development times, and allows you to concentrate on the core functions of the system design.
Stratix® V (GX, GS, and GT), Stratix IV (GX and GT), and Cyclone IV GX (F23 and larger packages), Stratix II GX, and Arria® series FPGAs and HardCopy IV GX ASICs provide a fully integrated XAUI solution for high-performance applications. This solution is designed to the IEEE 802.3 10-Gbps Ethernet standard. It utilizes built-in transceivers to implement the XAUI protocol in a single device. Additionally, for applications requiring 20-Gbps throughput, Altera's XAUI PHY solution can support DXAUI (4 x 6.25 Gbps) implementations on Stratix IV (GX and GT) FPGAs.
Table 1 provides an overview of the complete XAUI solution.
| Table 1. Complete XAUI Solution | |
| Solution | Description |
|---|---|
| Transceiver | Integrated XAUI-compliant transceivers arranged in blocks |
| Supported data rates | 3.125 Gbps, 3.75 Gbps, 6.25 Gbps |
| Altera IP | Altera 10-Gbps Ethernet Media Access Controller (MAC) MegaCore Function |
| Partner IP | MorethanIP 10GbE IP cores |
| Development boards | PCI Express® Development Kit, Stratix II GX Edition |
| Reference designs | 10-Gbps Ethernet Hardware Demonstration Reference Design |
| XAUI characterization report | Contact your local Altera sales representative |
Technology Background
Altera's Stratix V (GX, GS, and GT), Stratix IV (GX and GT), Cyclone IV GX, Stratix II GX, Arria series, and HardCopy IV GX devices are equipped with built-in transceivers that provide a dedicated mode for implementing the XAUI interface and allow the integration of multiple 10GbE PHYs and MACs into a single device. Embedded within the transceivers are dedicated rate-matching and clock compensation FIFO buffers, 8B/10B encoders and decoders, and word-alignment functions, all controlled by dedicated XAUI state machines. Each group of four channels also has built-in channel alignment circuitry to minimize skew across the XAUI interface from XAUI source to sink. Figure 1 shows the 10GbE MAC with integrated physical coding sublayer (PCS) block diagram interfacing with various 10GbE PHY devices and pluggable module options.
Figure 1. 10GbE MAC with Integrated PCS and PMA (PHY) Block Diagram
Notes:
- SPI = serial peripheral interface
- SFP = small form factor pluggable module
- MDIO = management data input/output (optional)
- XFP = 10 Gigabit Small Form Factor Pluggable module
- XFI = 10G Ethernet XFI
- SFP+ = 8.5- and 10-Gbps small form factor pluggable module
- SFI = SFP+ high-speed serial electrical interface
The transceiver module in Stratix V (GX, GS, and GT), Stratix IV (GX and GT), Cyclone IV GX (F23 and larger packages), HardCopy IV GX, Arria II GX, Stratix II GX, and Arria GX devices meet all IEEE 802.3 specifications, including jitter generation under 0.35 unit interval (UI) without pre-emphasis and jitter tolerance of more than 0.60 UI, peak-to-peak total. The transceiver module matches the IEEE 802.3 sinusoidal jitter-tolerance mask requirement. The 3.125-Gbps x4 channel unidirectional data transfer rate for 10GbE complies with the IEEE 802.3 XAUI definitions for linking physical-layer devices with upper-layer devices.
The XAUI transceiver module provides a 156.25-MHz input reference clock and parallel interface along with a
4-channel clock data recovery (CDR) receiver and 4-channel transceiver arrays, an AC-coupled differential interface, and differential pseudo current mode logic (PCML) drivers. The transceiver module also incorporates a 1:16 serializer/deserializer (SERDES) with a 16:20 gearbox, 8B/10B coding, and lane alignment. The transceivers offer up to 500 percent pre-emphasis and up to 17-dB equalization to compensate high-frequency losses.
Altera offers an array of silicon-proven 10GbE MAC cores with built-in support for the XGMII and XAUI, XSBI (64B/66B PCS layer) interfaces, and OC-192. Built-in support is also provided for flow control, MII management, address-based filtering, and statistics counters for RMON and MIB. The 10GbE MAC layer and reconciliation sublayer core is compliant with the IEEE 802.3 specification and supports multiple custom switch fabric enhancements to interface Altera's devices with 3.125-Gbps serial transceivers directly to 10GbE switch devices.
Altera is the first FPGA vendor to deliver a multi-gigabit and 10GbE PCI Express host adapter card development kit. The host bus adapter, called the Stratix IV GX FPGA Development Kit, is built with Altera's Stratix IV GX EP4SGX230 FPGA, with up to 36 multi-gigabit transceivers accelerating the convergence of network and storage applications using 10GbE technology.
Ethernet is the most popular LAN technology expanding into the metro and WAN networks, and it is the dominant wired networking protocol. It has evolved from a 1-MHz shared medium signal running on coaxial cable to the present availability of numerous variants operating as fast as 10 Gbps. Altera's 10GbE solutions provide top-of-the-line performance for leading-edge network development.
