Stratix II GX Signal Integrity Features

Managing signal integrity is critical for meeting or exceeding BER (Bit Error Ratio) performance specifications. Standard FR-4 printed circuit board (PCB) material can be very lossy at frequencies above 1GHz, yet, for many applications, it is a constraining choice due to its low material cost, high manufacturing yield and availability.

Stratix^® II GX FPGAs simplify the challenges of designing for signal integrity by providing transceivers with the best-in-class jitter characteristics and by having advanced features in their transceivers that simplify PCB design and that compensate for inevitable board losses. The advanced signal integrity features of Stratix II GX transceivers enable 6.375 Gbps operation across 1.25m of a Molex backplane that uses FR-4 (FR-408) PCB material. These signal integrity features may also allow Stratix II GX FPGAs to operate in legacy systems at higher data rates than initially intended, and have been demonstrated to allow error free operation for over a week on 30m of PCIe cabling at 2.5Gbps.

The Stratix II GX family of FPGAs are the only devices in the industry that have the ability to automatically and continuously monitor and set the equalizer to the best eye opening for a particular high-speed interconnect. Altera’s adaptive dispersion compensation engine (ADCE) technology now allows you the possibility of having one FPGA image for all card slots in your system, reducing inventory, characterization, and factory test costs. ADCE in production can continuously monitor and compensate for manufacturing variations as well as process voltage, and temperature effects.

Signal Integrity Features of Stratix II GX Transceiver FPGAs

Table 1 provides an overview of signal integrity features in Stratix II GX FPGAs.

Feature	Specification	Benefit
*Table 1. Stratix II GX Transceiver FPGAs Signal Integrity Enhancements*
Receiver Equalization	17 dB 4-Stage Filter	Delivers best-in-class signal integrity, enabling operation to 6.375 Gbps across 20-inches of FR-4 PCB material when used alone, or 1.25m on backplanes with pre-emphasis 30m of PCIe cable demonstrated low BER at 2.5Gbps with pre-emphasis Enables speed increases in legacy systems where loss is <17dB at F_NYQUIST Can either be set manually, or by using ADCE adaptive equalizer which monitors and continuously updates equalizer settings for the best eye opening
Programmable V_OD	400mV – 1400mV	Enables user to select level for system design or to meet protocol standard
Pre-Emphasis	500% 3-Taps	Delivers improved signal integrity, allowing 6.375 Gbps across 50-inches of FR-4 PCB material Enables legacy systems to run faster
On-Chip Termination	0, 100, 150 Differential	Simplifies board layout Removes need for additional PCB trace stubs

Pre-emphasis, equalization and V_OD are all dynamically programmable in Stratix II GX FPGAs. This allows you to change levels while the transceiver is operating, making it simpler to tune the interface for interoperability testing or change a setting depending on a board's location in a system.

Signal Integrity Features of the General FPGA Architecture

Table 2 provides a list of the signal integrity features added to Stratix II and Stratix II GX devices to support the FPGA architecture.

Feature	Specification	Benefit
*Table 2. Stratix II GX FPGA Architecture Signal Integrity Enhancements*
Dynamic Phase Alignment (DPA)	Source Synchronous I/O Operate to 1.25 Gbps	Compensates for skew in board layout allowing source synchronous I/O to operate at higher data rates Increases likelihood of successful PCB layout
Enhanced SSN Support	Increase Power/Ground/Pin Ratio Enhanced package design	Reduces the risk of SSN due to high edge-rate signals when using high-speed bus interfaces Stratix II GX FPGAs provide even greater signal, I/O pin, and ground ratio to counter additional transceiver requirements

More information on general FPGA architectural signal integrity issues can be found at the Signal Integrity Center.

Simulation

Simulations are a key element of high-speed board design. Simulations reduce risk, reduce the need for multiple PCB revisions, and ensure the system performs at optimum speed. To support the simulation process, Altera provides models and design-in kits for leading third-party EDA simulation and PCB layout tools. The models accurately reflect the operation of the Stratix II GX device transceiver buffers, allowing users to select the correct level of pre-emphasis, equalization and V_OD to meet their system requirements. Models and design-in kits include:

IBIS Models
SPICE Models (1)
Pre-emphasis and Equalization Link Estimator (PELE)
Transceiver ELDO Model
Silicon Design in Kit for Cadence Allegro PCB SI Platform
Silicon Design in Kit for Mentor Hyperlynx Platform
Silicon Design in Kit for Mentor ICX Platform

Design-in kits are available for the Cadence Allegro platform and the Mentor Graphics^® ICX and Hyperlynx tools. The kits contain validated models, topology files, layout constraints, example PCB files and footprints, tutorials, documentation, scripts, and other utilities.

Notes

(1) HSPICE models require an NDA. Please contact your local Altera^® FAE to obtain HSPICE models

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